Exemplary embodiments of the present invention relate to an integrated circuit, and more particularly, to an integrated circuit for generating an internal voltage.
An integrated circuit receives an external voltage, generates internal voltages having various voltage levels, and forms an internal circuit using these internal voltages.
FIG. 1 is a circuit diagram illustrating a conventional integrated circuit.
Referring to FIG. 1, the conventional integrated circuit includes a power-up signal generating unit 11, a first internal voltage generating unit 12 and a second internal voltage generating unit 13.
The power-up signal generating unit 11 generates a power-up signal PWRUP in response to a voltage level of a power supply voltage VDD provided by an external power supply. For reference, the power-up signal PWRUP is activated when the power supply voltage VDD exceeds a predetermined voltage level.
The first internal voltage generating unit 12 receives a ground voltage VSS and the power-up signal PWRUP, and generates a first internal voltage VINT1 in response to the power-up signal PWRUP. That is, when the power-up signal PWRUP is activated, the first internal voltage VINT1 is generated.
The first internal voltage generating unit 12 includes an internal voltage level detecting block 121, a periodic pulse generating block 122, and a charge pumping block 123.
The internal voltage level detecting block 121 detects whether the first internal voltage VINT1 is a target voltage, and outputs a voltage detection signal V_DET. The periodic pulse generating block 122 receives the voltage detection signal V_DET and the power-up signal PWRUP, and generates a periodic pulse signal OSC in response to the voltage detection signal V_DET and the power-up signal PWRUP. The charge pumping block 123 receives the periodic pulse signal OSC, and utilizes the ground voltage VSS to generate the first internal voltage VINT1 by performing a charge pumping operation in response to the periodic pulse signal OSC.
When the power-up signal PWRUP is activated, the periodic pulse generating block 122 outputs the periodic pulse signal OSC having a specific period, and the charge pumping block 123 generates the first internal voltage VINT1 using the periodic pulse signal OSC.
The second internal voltage generating unit 13 receives the first internal voltage VINT1 as a driving power and generates a second internal voltage VINT2 higher than the first internal voltage VINT1 in response to the power-up signal PWRUP.
Herein, the first internal voltage VINT1 is a negative voltage. Before the power-up signal PWRUP is activated, the ground voltage VSS is transferred to a first negative voltage terminal VBB through a first NMOS transistor MN1. After the power-up signal PWRUP is activated, the first internal voltage VINT1 is transferred to the first negative voltage terminal VBB.
Further, the second internal voltage VINT2 is a negative voltage. Before the power-up signal PWRUP is activated, the ground voltage VSS is transferred to a second negative voltage terminal VBBW through a second NMOS transistor MN2. After the power-up signal PWRUP is activated, the first internal voltage VINT1 is transferred to the second negative voltage terminal VBBW.
FIG. 2 is a graph illustrating a voltage change according to an internal operation of an integrated circuit shown in FIG. 1.
Referring to FIG. 2, before the power-up signal PWRUP is activated, the first negative voltage terminal VBB and the second negative voltage terminal VBBW maintain a ground voltage. After the power supply voltage VDD exceeds a predetermined voltage level, the power-up signal PWRUP is shifted to a low level voltage and is activated.
If the power-up signal PWRUP is activated, the first internal voltage generating unit 12 generates and transfers the first internal voltage VINT1 to the first negative voltage terminal VBB, and the second internal voltage generating unit 13 generates the second internal voltage VINT2 using the first internal voltage VINT1 and transfers the second internal voltage VINT2 to the second negative voltage terminal VBBW.
Meanwhile, the second internal voltage VINT2 is generated using the first internal voltage VINT1 as an operating power voltage. Accordingly, if a large amount of the second internal voltage VINT2 is consumed before the first internal voltage VINT1 is stabilized, the second internal voltage VINT2 increases up to a voltage level of a ground voltage VSS, and therefore, the first internal voltage VINT1 may also increase up to the voltage level of the ground voltage VSS. As described above, if an internal voltage is unstable, an internal circuit using the internal voltage may malfunction.